== Question ==

What is the right level of filtering at each level of the hierarchy?


== Summary ==

Each layer of our hierarchy works on different time scales (e.g. circuits on the time scale of gate delays, microarchitecture on the timescale of cycles to tens of cycles, system software on the timescale of millions of cycles).  Higher level, infrequent handling can be efficient, if errors don't occur too often.  To make sure this is the case, lower levels must filter adequately.  If the software takes millions of cycles to respond to an error, but errors are occurring every 10,000 cycles, it won't be able to keep up---some layer below it must filter out most of the errors.

== Subquestions ==
   
  * How do we characterize and assess the filtering? 
  * How do we tune and validate filtering?
  * ''add refinements/subquestions here''


== Relevant Scenarios ==

  * Conventional DRAM memory system employ a combination of device hardening (device level), ECC (circuit level), and scrubbing (sometimes performed at software or OS level).  ECC circuitry means software handling does not get involved on every word read, or even on every corrected bit error.

 * [[Scenarios/S1|Scenario 1]]

== Workshop Materials ==

 * [[attachment:Meetings/First/Program/filter.pdf|Workshop 1 Slides]]

== Existing Work ==


 * ''add additional references here''

== Comments ==

 * ''To comment, please add another bullet to this list.''