Charge to ''insert-group'' Constituency (DRAFT)

Articulate a quantifiable challenge goal for your problem domain. The goal should include a clear identification of where we are and how much better things need to become.

The goal should represent something that, if obtained, the industry and community would recognize as a major accomplishment.
The goal (or progress toward the goal) should be a reasonable target (perhaps stretch target) for research efforts.

Uses

Polished versions may provide direct guidance to funding agencies on where to set goals.
It is necessary to show that there is a room for improvement and a need for it to make a strong case for funding.
Quantitative goals help demonstrate this is a rigorous scientific endeavor and a program can make solid, lasting progress---rather than just being a collection of projects (hacks) that do not add up.
Goals should inspire students
- attract smart people to the field
- help them see there are interesting problems where they can make an impact
- help them see how advances here make the world better (impact people's lives)

Our {devices,components,systems} in our target environment (in future technology X?) see upset rate A (unpredictability, wearout, etc. --- see metrics challenge).
Unmitigated we see the systems we want to build will have FIT rate B (or other appropriate badness metrics --- see metrics challenge)
We need to achieve FIT rate C (or other appropriate metric)
With current state of the art, it requires overhead D to achieve FIT rate C.
This is bad for reasons Y, Z....
If we could reduce the overhead from D to E, many great things will occur.
- (explain how great things increase the spread of happiness, wealth, freedom, democracy, and health)

Increasing variation of small scale devices leads to variations exceeding 30% (sigma>30% nominal) by the 22nm node. Unmitigated, this will lead to chip yields that are unacceptably low. We need >90% chip yields and the ability to continue to scale down operating voltages (perhaps quantify scaling rate goal). Current approaches of voltage margining will demand increases in operating voltages to achieve this yield. This negates the traditional benefits of scaling, both increasing the energy per operation (assuming V increase is larger than capacitive saving) and preventing us from delivering higher computation/time/cm² (due to limited power budgets on a chip -- e.g. 100W/cm²) meaning there would be no net benefit to continued feature size scaling. If we could reduce or negate the voltage margin costs (allowing voltage to continue to scale down by XXX and achieving within 10% energy of an ideal technology with sigma<5%), scaling could continue at least until F=5nm (another order of magnitude in linear feature sizes).

It may be useful to identify a benchmark or set of benchmarks that this community agrees will demonstrate and motivate the issues and would be suitable vehicles against which to measure progress on the quantitative goals.

Metrics and roadmap efforts are intended to complement this effort providing guidance on best practices for characterizing the noisiness of technology/environments and the reliability of systems (metrics) and a plausible scenario for the increase of noise-effects with technology scaling (roadmap).